Automatic Abstraction for Verification of Timed Circuits and Systems?
Abstract
This paper presents a new approach for verification of asynchronous circuits by using automatic abstraction. It attacks the state explosion problem by avoiding the generation of a flat state space for the whole design. Instead, it breaks the design into blocks and conducts verification on each of them. Using this approach, the speed of verification improves dramatically.
Type
Publication
Computer Aided Verification
Hao Zheng
University of South Florida, Associate Professor
Eric Mercer
Brigham Young University, Associate Professor
